Generally, as shown in FIG. 21, an image display device such as a liquid crystal panel and an organic EL (Electroluminescence) panel includes: data signal lines SL1 to SLx; scanning signal lines GL1 to GLy which cross the data signal lines SL1 to SLx at a right angle; a pixel array PIXARRAY having pixels PIX disposed on intersections of the data signal lines and the scanning signal lines; a data signal line driving circuit SD for driving the data signal lines; a scanning signal line driving circuit GD for driving the scanning signal lines; and a control signal generating section for supplying a control signal to the data signal line driving circuit SD and the scanning signal line driving circuit GD.
The data signal line driving circuit SD, the scanning signal line driving circuit GD, the control signal generating section, and the pixel array PIXARRAY are integrally formed on an insulating substrate made of material such as glass, quartz, and the like. In this case, each of the driving circuits is constituted of a thin film MOS transistor made of poysilicon (hereinafter, referred to as a polysilicon TFT).
Incidentally, a driving circuit using a polysilicon TFT has such disadvantage that its operation speed is much slower than that of a driving circuit using a monocrystal silicon TFT. Particularly, in a case of realizing large-screen and large-volumetric display by using the data signal line driving circuit for driving the data signal lines, a shift resister which constitutes the data signal line driving circuit operates too slowly. Thus, various methods are studied to drive the data signal line within the operation speed of the shift resister constituted of the polysilicon TFT.
For example, there is proposed the following multiphase development technique: in the data signal line driving circuit, a plurality of video signal lines are provided, and a multiphased video signal DAT is inputted to the video signal lines, and the video signal inputted to one video signal and the video signal inputted to another video signal line are simultaneously outputted from the data signal lines connected to the video signal lines, thereby dropping a frequency of the shift resister as the video signal is further multiphased.
FIG. 22 is a block diagram schematically showing the data signal line driving circuit in a case where a video signal is two-phased. In this example, the video signal DAT is divided into two video signals: a video signal DAT1 and a video signal DAT2, and the video signals DAT1 and DAT2 are outputted from the data signal lines via the respective video signal lines. In this case, as shown in FIG. 23, two data signal lines SL are driven at the same timing by a single shift resister SR and a single waveform shaping circuit SMP (see a timing chart shown in FIG. 24).
Note that, FIG. 22 illustrates (i) two video signal lines and (ii) a single shift resister corresponding to the two video signal lines, so as to simplify the illustration, but a technique, based on the same technical idea, which has eight video signal lines and four shift resisters corresponding to the four video signal lines, is disclosed in Patent Document 1 (U.S. Pat. No. 6,219,023 B1) for example.
As described above, when the data signal line driving circuit is driven in accordance with two-phase development, it is possible to slow an operation speed (frequency) of a shift resister constituting the data signal line driving circuit.
Note that, FIG. 24 is a timing chart showing a case where it is assumed that resolution of the pixel PIXARRAY which functions as a display section is the same as resolution of the inputted video signal.
However, in the foregoing display device, it is required that the resolution of the display section is the same as the resolution of the video signal, and it is also required to input the video signal whose resolution is less than the resolution of the display section so as to display an image. For example, in order to display an image appropriately in inputting the video signal whose resolution is half of the resolution of the display section, the data signal line driving circuit is operated in accordance with the timing chart shown in FIG. 25. That is, by causing two data signal lines to output the same video signal, it is possible to display the video signal whose resolution is half of the resolution of the display section. Note that, at this time, also in the scanning line driving circuit, every two scanning signal lines are driven.
Incidentally, in a conventional data signal line driving circuit which performs multiphase development, the data signal lines adjacent to each other are respectively connected to the video signal lines different from each other. For example, in a case of a data signal line driving circuit shown in FIG. 22, two data signal lines adjacent to each other are respectively connected to the video signal lines DAT1 and DAT2. Moreover, the two data signal lines adjacent to each other are connected to the same shift resister SR via the same waveform shaping circuit SMP.
Thus, when displaying the video signal whose resolution is the same as the resolution of the display section (high resolution driving), as shown in FIG. 24, the video signals from the two video signal lines are outputted to the data signal line in synchronism with a timing pulse from the shift resister, so that the development is performed in accordance with two-phase development. Thus, it is possible to make the frequency of the shift resister half of the frequency in the case where the phase development is not performed while keeping the frequency of the video signal as it is. As a result, it is possible to obtain such advantage that power consumption of the data signal line driving circuit can be reduced compared with the case where the phase development is not performed.
However, when displaying the video signal whose resolution is lower than the resolution of the display section (low resolution driving), as shown in FIG. 25, the same video signal is supplied to the data signal lines adjacent to each other, so that it is necessary to supply the same video signal to the two video signal lines. Thus, in performing the low resolution driving, the phase development is not performed unlike the high resolution driving.
In this manner, when the low resolution driving is performed, as described above, it is necessary to supply the same data to the two video signal lines, so that the frequency of the shift resister of the data signal line driving circuit shown in FIG. 22 is the same as the frequency in the case where the high resolution driving is performed, but the frequency of the video signal supplied from the video signal line is also the same as the frequency in the case where the high resolution driving is performed. As a result, the power consumption etc. in the data signal line driving circuit is equal to the power consumption etc. in the case where the high resolution driving is performed. As a result, the power consumption of the data signal line driving circuit in performing the low resolution driving is equal to the power consumption of the data signal line driving circuit in performing the high resolution driving.
Thus, in the conventional data signal line driving circuit which performs the multiphase development, the power consumption etc. in the case where the high resolution driving is equal to the power consumption etc. in the case where the low resolution driving is performed, so that this raises such problem that the power consumption is not reduced even when the resolution is lowered.